The present invention relates to a data processing system, and particularly to a technique useful in application to a data processing system which requires a low power consumption.
To materialize a desired function, a data processing system such as a portable terminal device (terminal device) or a server is arranged by mutually connecting a plurality of electronic components such as a microcontroller, a memory, a sensor and a power source IC. In such a data processing system, e.g. a microcontroller appropriately executes an interrupt process in response to an interrupt request from a sensor, a power source IC, or the like while controlling the whole system. For instance, the Japanese Unexamined Patent Application Publication No. JP-A-2009-175971 discloses a microcontroller which performs scheduling so as to execute, by priority, a periodic task for control even if an interrupt by a task for information occurs.
Meanwhile, the need for power saving in a data processing system has been increasing in recent years. To achieve the power saving in a data processing system, it is essential to suppress the power consumption by individual semiconductor integrated circuits forming the data processing system. In recent years, a technique called “power gating” attracts attention as a technique for power saving of semiconductor integrated circuits. The power gating is a method for reducing the power consumption of a semiconductor integrated circuit on the whole by which a leak current of a circuit block concerned is suppressed by cutting off the power supply to the circuit block which does not work in the semiconductor integrated circuit.
Examples of such technique have been disclosed. One of them is a technique in connection with SOC (System-on-a-chip) for mobile use applicable to a portable terminal device (or a terminal device) and the like for cutting off a power supply to a circuit block (e.g. IP) which does not work according to the action mode of a portable terminal device (or a terminal device), which has been disclosed by: T. Hattori, et. al., “Hierarchical power distribution and power management scheme for a single chip mobile processor”, Proc. of DAC, pp. 292-295, 2006.
Another example is a technique for cutting off a power source at the level of an operational device inside CPU by using, as conditional branches, an instruction set level, a cache miss action and the like, which has been disclosed by: D. Ikebuchi and et. al., “Geyser-1: A mips r3000 cpu core with fine grain runtime power gating,” IEEE Asian Solid-State Circuits Conference Nov. 16-18, 2009, Taipei, Taiwan.